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general description the MAX5853 dual, 10-bit, 80msps digital-to-analog converter (dac) provides superior dynamic performance in wideband communication systems. the device inte- grates two 10-bit dac cores, and a 1.24v reference. the converter supports single-ended and differential modes of operation. the MAX5853 dynamic performance is maintained over the entire 2.7v to 3.6v power-supply operating range. the analog outputs support a -1.0v to +1.25v compliance voltage. the MAX5853 can also operate in interleave data mode to reduce the i/o pin count. this allows the converter to be updated on a single, 10-bit bus. the MAX5853 features digital control of channel gain matching to within ?.4db in sixteen 0.05db steps. channel matching improves sideband suppression in analog quadrature modulation applications. the on- chip 1.24v bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. the internal ref- erence can be disabled and an external reference may be applied for high-accuracy applications. the MAX5853 features full-scale current outputs of 2ma to 20ma and operates from a 2.7v to 3.6v single supply. the dac supports three modes of power-control opera- tion: normal, low-power standby, and complete power- down. in power-down mode, the operating current is reduced to 1?. the MAX5853 is packaged in a 40-pin thin qfn with exposed paddle (ep) and is specified for the extended (-40? to +85?) temperature range. pin-compatible, higher speed, and lower resolution versions are also available. refer to the max5854 (10-bit, 165msps), the max5852** (8-bit, 165msps), and the max5851** (8-bit, 80msps) data sheets for more information. see table 4 at the end of the data sheet. applications communications satcom, lmds, mmds, hfc, dsl, wlan, point-to-point microwave links wireless base stations quadrature modulation direct digital synthesis (dds) instrumentation/ate features 10-bit, 80msps dual dac low power 77mw with i fs = 5ma at f clk = 80mhz 2.7v to 3.6v single supply full output swing and dynamic performance at 2.7v supply superior dynamic performance 78dbc sfdr at f out = 20mhz programmable channel gain matching integrated 1.24v low-noise bandgap reference single-resistor gain control interleaved data mode single-ended and differential clock input modes miniature 40-pin thin qfn package, 6mm x 6mm ev kit available?ax5854 ev kit MAX5853 dual, 10-bit, 80msps, current-output dac ________________________________________________________________ maxim integrated products 1 ordering information 19-3196; rev 0; 2/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. e v a l u a t i o n k i t a v a i l a b l e part temp range pin-package MAX5853etl -40 c to +85 c 40 thin qfn-ep* 40 36 37 38 39 ep 18 21 23 22 24 25 19 20 16 17 6 5 4 3 2 1 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 da0 db8 agnd MAX5853 thin qfn top view av dd outpa outna agnd outpb outnb av dd refr refo db9 db6 db7 dv dd db5 db4 dgnd db2 db3 cv dd cgnd clk cv dd clkxn clkxp dce cw db0 db1 da1 da2/g0 da3/g1 da4/g2 da5/g3 da6/ren da7/ide da8/dacen da9/pd pin configuration * ep = exposed paddle. ** future product?ontact factory for availability.
MAX5853 dual, 10-bit, 80msps, current-output dac 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 80msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, differential output, output amplitude = 0dbfs, t a = t min to t max , unless otherwise noted. t a +25 c, guaranteed by produc- tion test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +4v dv dd to dgnd.........................................................-0.3v to +4v cv dd to cgnd.........................................................-0.3v to +4v av dd to dv dd .............................................................-4v to +4v agnd to dgnd.....................................................-0.3v to +0.3v agnd to cgnd.....................................................-0.3v to +0.3v dgnd to cgnd ....................................................-0.3v to +0.3v da9 da0, db9 db0, cw , dce to dgnd ...............-0.3v to +4v clk to cgnd ..........................................-0.3v to (cv dd + 0.3v) clkxn, clkxp to cgnd.........................................-0.3v to +4v refr, refo to agnd .............................-0.3v to (av dd + 0.3v) outpa, outna to agnd ..........(av dd - 4.8v) to (av dd + 0.3v) outpb, outnb to agnd ..........(av dd - 4.8v) to (av dd + 0.3v) maximum current into any pin (excluding power supplies) ..........................................50ma continuous power dissipation (t a = +70 c) 40-pin thin qfn (derate 26.3mw/ c above +70 c)....2105mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units static performance resolution n 10 bits integral nonlinearity inl r l = 0 -1.0 0.25 +1.0 lsb differential nonlinearity dnl guaranteed monotonic, r l = 0 -0.5 0.2 +0.5 lsb offset error v os -0.5 0.1 +0.5 lsb internal reference (note1) -11.0 1.5 +6.8 gain error (see also gain error definition section) ge external reference -6.25 0.7 +4.10 %fsr internal reference 150 gain-error temperature drift external reference 100 ppm/ c dynamic performance f out = 10mhz 69.5 78 f out = 20mhz 78 f clk = 80mhz, a out = -1dbfs f out = 30mhz 72 f clk = 44mhz, a out = -1dbfs f out = 10mhz 78 spurious-free dynamic range to nyquist sfdr f clk = 25mhz, a out = -1dbfs f out = 1mhz 79 dbc f clk = 80mhz, f out = 10mhz, a out = -1dbfs, span = 10mhz 85 f clk = 65mhz, f out = 5mhz, a out = -1dbfs, span = 2.5mhz 82 spurious-free dynamic range within a window sfdr f clk = 25mhz, f out = 1mhz, a out = -1dbfs, span = 2mhz 82 dbc multitone power ratio to nyquist mtpr 8 tones at 400khz spacing, f clk = 78mhz, f out = 15mhz to 18.2mhz 74 dbc
MAX5853 dual, 10-bit, 80msps, current-output dac _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 80msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, differential output, output amplitude = 0dbfs, t a = t min to t max , unless otherwise noted. t a +25 c, guaranteed by produc- tion test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units multitone spurious-free dynamic range within a window 8 tones at 811kh z sp aci ng , f c lk = 80m h z, f ou t = 10.8m h z to 17.2m h z, sp an = 15m h z 76 dbc f out = 10mhz -76 f out = 20mhz -75 f clk = 80mhz, a out = -1dbfs f out = 30mhz -70 f clk = 44mhz, a out = -1dbfs f out = 10mhz -76 total harmonic distortion to nyquist (2nd- through 8th-order harmonics included) thd f clk = 25mhz, a out = -1dbfs f out = 1mhz -76 dbc output channel-to-channel isolation f out = 10mhz 90 db channel-to-channel gain mismatch f out = 10mhz, g[3:0] = 1000 0.025 db channel-to-channel phase mismatch f out = 10mhz 0.05 degrees f clk = 80mhz, f out = 5mhz, i fs = 20ma 62 signal-to-noise ratio to nyquist snr f clk = 80mhz, f out = 5mhz, i fs = 5ma 62 db interleaved mode disabled, ide = 0 80 maximum dac conversion rate f dac interleaved mode enabled, ide = 1 80 msps glitch impulse 5 pv-s output settling time t s to 0.1% error band (note 3) 12 ns output rise time 10% to 90% (note 3) 2.2 ns output fall time 90% to 10% (note 3) 2.2 ns analog output full-scale output current range i fs 220ma output voltage compliance range -1.00 +1.25 v output leakage current shutdown or standby mode -5 +5 a reference internal-reference output voltage v refo ren = 0 1.13 1.24 1.32 v internal-reference supply rejection av dd varied from 2.7v to 3.6v 0.5 mv/v internal-reference output- voltage temperature drift tcv refo ren = 0 50 ppm/ c
MAX5853 dual, 10-bit, 80msps, current-output dac 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 80msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, differential output, output amplitude = 0dbfs, t a = t min to t max , unless otherwise noted. t a +25 c, guaranteed by produc- tion test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units internal-reference output drive capability ren = 0 50 a external-reference input voltage range ren = 1 0.10 1.2 1.32 v current gain i fs /i ref 32 ma/ma logic inputs (da9 da0, db9 db0, cw ) digital input-voltage high v ih 0.65 x dv dd v digital input-voltage low v il 0.3 x dv dd v digital input current i in -1 +1 a digital input capacitance c in 3pf single-ended clock input/output and dce input (clk, dce ) digital input-voltage high v ih dce = 1 0.65 x cv dd v digital input-voltage low v il dce = 1 0.3 x cv dd v digital input current i in dce = 1 -1 +1 a digital input capacitance c in dce = 1 3 pf digital output-voltage high v oh dce = 0, i source = 0.5ma, figure 1 0.9 x cv dd v digital output-voltage low v ol dce = 0, i sink = 0.5ma, figure 1 0.1 x cv dd v differential clock inputs (clkxp/clkxn) differential clock input internal bias cv dd / 2 v differential clock input swing 0.5 v clock input impedance measured single ended 5 k ? power requirements analog power-supply voltage av dd 2.7 3 3.6 v digital power-supply voltage dv dd 2.7 3 3.6 v clock power-supply voltage cv dd 2.7 3 3.6 v i fs = 20ma (note 2), single-ended clock mode 43.2 46 i fs = 20ma (note 2), differential clock mode 43.2 i fs = 2ma (note 2), single-ended clock mode 5 analog supply current i avdd i fs = 2ma (note 2), differential clock mode 5 ma
MAX5853 dual, 10-bit, 80msps, current-output dac _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 80msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, differential output, output amplitude = 0dbfs, t a = t min to t max , unless otherwise noted. t a +25 c, guaranteed by produc- tion test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units i fs = 20ma (note 2), single-ended clock mode 3.4 4 digital supply current i dvdd i fs = 20ma (note 2), differential clock mode 3.4 ma single-ended clock mode ( dce = 1) (note 2) 11.1 13.5 clock supply current i cvdd differential clock mode ( dce = 0) (note 2) 16.7 ma total standby current i standby i avdd + i dvdd + i cvdd 3.1 3.7 ma total shutdown current i shdn i avdd + i dvdd + i cvdd 1a i fs = 20ma (note 2) 173 191 single-ended clock mode ( dce = 1) i fs = 2ma (note 2) 58 i fs = 20ma (note 2) 190 differential clock mode ( dce = 0) i fs = 2ma (note 2) 75 standby 9.3 11.1 total power dissipation p tot shutdown 0.003 mw timing characteristics (figures 5 and 6) propagation delay 1 clock cycles s i ng l e- end ed cl ock m od e ( d ce = 1) ( n ote 4) 1.2 dac data to clk rise/fall setup time t dcs differential clock mode ( dce = 0) (note 4) 2.7 ns s i ng l e- end ed cl ock m od e ( d ce = 1) ( n ote 4) 0.8 dac data to clk rise/fall hold time t dch differential clock mode ( dce = 0) (note 4) -0.5 ns control word to cw rise setup time t cs 2.5 ns control word to cw rise hold time t cw 2.5 ns cw high time t cwh 5ns cw low time t cwl 5ns
MAX5853 dual, 10-bit, 80msps, current-output dac 6 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 80msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, differential output, output amplitude = 0dbfs, t a = t min to t max , unless otherwise noted. t a +25 c, guaranteed by produc- tion test. t a < +25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units dacen = 1 to v out stable time (coming out of standby) t stb 3s pd = 0 to v out stable time (coming out of power-down) t shdn 500 s maximum clock frequency at clkxp/clkxn input f clk 80 mhz clock high time t cxh clkxp or clkxn input 3 ns clock low time t cxl clkxp or clkxn input 3 ns clkxp rise to clk output rise delay t cdh dce = 0 2.7 ns clkxp fall to clk output fall delay t cdl dce = 0 2.7 ns note 1: including the internal reference voltage tolerance and reference amplifier offset. note 2: f dac = 80msps, f out = 10mhz. note 3: measured single ended with 50 ? load and complementary output connected to ground. note 4: guaranteed by design, not production tested. to output pin 5pf 0.5ma 0.5ma 1.6v figure 1. load test circuit for clk outputs
MAX5853 dual, 10-bit, 80msps, current-output dac _______________________________________________________________________________________ 7 spurious-free dynamic range vs. output frequency (f clk = 80mhz) MAX5853 toc01 f out (mhz) sfdr (dbc) 35 30 20 25 10 15 5 35 40 45 50 55 60 65 70 75 80 85 90 30 040 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 44mhz) MAX5853 toc02 f out (mhz) sfdr (dbc) 20 18 14 16 4 6 8 10 12 2 35 40 45 50 55 60 65 70 75 80 85 90 30 022 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 25mhz) MAX5853 toc03 f out (mhz) sfdr (dbc) 11 9 7 5 3 35 40 45 50 55 60 65 70 75 80 85 90 30 113 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 65mhz) MAX5853 toc04 f out (mhz) sfdr (dbc) 30 25 15 20 10 5 35 40 45 50 55 60 65 70 75 80 85 90 30 035 0dbfs -12dbfs -6dbfs spurious-free dynamic range vs. output frequency (f clk = 80mhz) MAX5853 toc05 f out (mhz) sfdr (dbc) 35 30 20 25 10 15 5 35 40 45 50 55 60 65 70 75 80 85 90 30 040 i out = 20ma i out = 10ma i out = 5ma spurious-free dynamic range vs. output frequency (f clk = 80mhz) MAX5853 toc06 f out (mhz) sfdr (dbc) 35 30 5 10 15 20 25 55 60 65 70 75 80 85 90 50 040 av dd = dv dd = cv dd = 2.7v av dd = dv dd = cv dd = 3.6v av dd = dv dd = cv dd = 3v av dd = dv dd = cv dd = 3v spurious-free dynamic range vs. temperature (f clk = 80mhz, f out = 10mhz, a out = 0dbfs) MAX5853 toc07 temperature ( c) sfdr (dbc) 60 35 -15 10 76 77 78 79 80 81 82 83 75 -40 85 typical operating characteristics (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, external reference, i fs = 20ma, differential output, differential clock (unless otherwise noted), t a = +25 c.) two-tone intermodulation distortion (f clk = 80mhz, 8mhz window) MAX5853 toc08 f out (mhz) amplitude (db) 10.5 9.5 7.5 8.5 5.5 6.5 4.5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 3.5 11.5 f out1 = 8.2519mhz f out2 = 8.7030mhz f out1 f out2 2f out1 - f out2 2f out2 - f out1
MAX5853 dual, 10-bit, 80msps, current-output dac 8 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, external reference, i fs = 20ma, differential output, differential clock (unless otherwise noted), t a = +25 c.) single-tone sfdr (f clk = 80mhz, 10mhz window) MAX5853 toc10 f out (mhz) amplitude (db) 13 11 9 7 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 515 f out = 10.0572mhz a out = -1dbfs single-tone sfdr (f clk = 25mhz, 2mhz window) MAX5853 toc11 f out (mhz) amplitude (db) 1.7 1.3 0.9 0.5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 100 0.1 2.1 f out = 1.0132mhz a out = -1dbfs single-tone sfdr (f clk = 65mhz, 2.5mhz window) MAX5853 toc12 f out (mhz) amplitude (db) 5.8 5.3 4.8 4.3 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 3.8 6.3 f out = 4.9901mhz a out = -1dbfs single-tone fft plot (f clk = 80mhz, nyquist window) MAX5853 toc13 output tone frequency (mhz) amplitude (db) 3.95mhz/div -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.5 40 f out = 10mhz a out = 0dbfs 8-tone sfdr plot (f clk = 80mhz, 15mhz window) MAX5853 toc09 f out (mhz) amplitude (db) 18.5 15.5 12.5 9.5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 6.5 21.5 f t4 f t3 f t2 f t1 f t5 f t6 f t7 f t8 f t1 = 10.825mhz f t2 = 11.475mhz f t3 = 12.425mhz f t4 = 13.175mhz f t5 = 14.825mhz f t6 = 15.675mhz f t7 = 16.475mhz f t8 = 17.375mhz
MAX5853 dual, 10-bit, 80msps, current-output dac _______________________________________________________________________________________ 9 reference voltage vs. temperature MAX5853 toc19 temperature ( c) reference voltage (v) 60 35 10 -15 1.20 1.21 1.22 1.23 1.24 1.25 1.19 -40 85 dynamic response rise time MAX5853 toc20 100mv/div 10ns/div dynamic response fall time MAX5853 toc21 100mv/div 10ns/div spurious-free dynamic range vs. output frequency (f clk = 80mhz) MAX5853 toc22 f out (mhz) sfdr (dbc) 35 30 20 25 10 15 5 35 40 45 50 55 60 65 70 75 80 85 90 30 040 0dbfs -6dbfs -12dbfs single-ended clock drive typical operating characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, external reference, i fs = 20ma, differential output, differential clock (unless otherwise noted), t a = +25 c.) integral nonlinearity vs. digital input code MAX5853 toc14 digital input code inl (lsb) 900 750 450 600 300 150 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 1050 differential nonlinearity vs. digital input code MAX5853 toc15 digital input code dnl (lsb) 900 750 450 600 300 150 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 1050 power dissipation vs. clock frequency (f out = 10mhz, a out = 0dbfs) MAX5853 toc16 f clk (mhz) power dissipation (mw) 75 70 65 60 55 50 45 40 35 30 25 150 160 170 180 190 200 140 20 80 differential clock drive single-ended clock drive power dissipation vs. supply voltages (f clk = 80mhz, f out = 10mhz) MAX5853 toc17 supply voltages (v) power dissipation (mw) 3.45 3.30 3.15 3.00 2.85 150 160 170 180 190 200 210 220 230 240 250 140 2.70 3.60 differential clock drive single-ended clock drive reference voltage vs. supply voltages (f clk = 80mhz, f out = 10mhz) MAX5853 toc18 supply voltages (v) reference voltage (v) 3.45 3.30 3.15 3.00 2.85 1.22670 1.22690 1.22710 1.22730 1.22750 1.22650 2.70 3.60
MAX5853 dual, 10-bit, 80msps, current-output dac 10 ______________________________________________________________________________________ pin description pin name function 1 da9/pd channel a input data bit 9 (msb)/power-down 2 da8/dacen channel a input data bit 8/dac enable control 3 da7/ide channel a input data bit 7/interleaved data enable 4 da6/ ren channel a input data bit 6/reference enable. setting ren = 0 enables the internal reference. setting ren = 1 disables the internal reference. 5 da5/g3 channel a input data bit 5/channel a gain adjustment bit 3 6 da4/g2 channel a input data bit 4/channel a gain adjustment bit 2 7 da3/g1 channel a input data bit 3/channel a gain adjustment bit 1 8 da2/g0 channel a input data bit 2/channel a gain adjustment bit 0 9 da1 channel a input data bit 1 10 da0 channel a input data bit 0 (lsb) 11 db9 channel b input data bit 9 (msb) 12 db8 channel b input data bit 8 13 db7 channel b input data bit 7 14 db6 channel b input data bit 6 15 db5 channel b input data bit 5 16 dv dd d i g i tal p ow er inp ut. s ee the p ow er s up p l i es, byp assi ng , d ecoup l i ng , and layout secti on for m or e d etai l s. 17 dgnd digital ground 18 db4 channel b input data bit 4 19 db3 channel b input data bit 3 20 db2 channel b input data bit 2 21 db1 channel b input data bit 1 22 db0 channel b input data bit 0 (lsb) 23 cw active-low control word write pulse. the control word is latched on the rising edge of cw . 24 dce active-low differential clock enable input. drive dce low to enable the differential clock inputs clkxp and clkxn. drive dce high to disable the differential clock inputs and enable the single- ended clk input. 25 clkxp positive differential clock input. with dce = 0, clkxp and clkxn are enabled. with dce = 1, clkxp and clkxn are disabled. connect clkxp to cgnd when the differential clock is disabled. 26 clkxn negative differential clock input. with dce = 0, clkxp and clkxn are enabled. with dce = 1, clkxp and clkxn are disabled. connect clkxn to cv dd when the differential clock is disabled. 27, 30 cv dd clock power input. see the power supplies, bypassing, decoupling, and layout section for more 28 clk single-ended clock input/output. with the differential clock disabled ( dce = 1), clk becomes a single-ended conversion clock input. with the differential clock enabled ( dce = 0), clk is a single- ended output that mirrors the differential clock inputs clkxp and clkxn. see the clock modes section for more information on clk. 29 cgnd clock ground 31 refo reference input/output. refo serves as a reference input when the internal reference is disabled. if the internal 1.24v reference is enabled, refo serves as an output for the internal reference. when the internal reference is enabled, bypass refo to agnd with a 0.1f capacitor
MAX5853 dual, 10-bit, 80msps, current-output dac ______________________________________________________________________________________ 11 detailed description the MAX5853 dual, high-speed, 10-bit, current-output dac provides superior performance in communication systems requiring low-distortion analog-signal recon- struction. the MAX5853 combines two dacs and an on- chip 1.24v reference (figure 2). the current outputs of the dacs can be configured for differential or single- ended operation. the full-scale output current range is adjustable from 2ma to 20ma to optimize power dissi- pation and gain control. the MAX5853 accepts an input data and a dac con- version rate of 80mhz. the inputs are latched on the rising edge of the clock whereas the output latches on the following rising edge. the MAX5853 features three modes of operation: normal, standby, and power-down (table 2). these modes allow efficient power management. in power-down, the MAX5853 consumes only 1a of supply current. wake- up time from standby mode to normal dac operation is 3s. programming the dac an 8-bit control word routed through channel a s data port programs the gain matching, reference, and the operational mode of the MAX5853. the control word is latched on the rising edge of cw . cw is independent of the dac clock. the dac clock can always remain running when the control word is written to the dac. table 1 and table 2 represent the control word format and function. the gain on channel a can be adjusted to achieve gain matching between two channels in a user s system. the gain on channel a can be adjusted from -0.4db to 0.35db in steps of 0.05db by using bits g3 to g0 (see table 3). pin description (continued) pin name function 32 refr full-scale current adjustment. to set the output full-scale current, connect an external resistor rset between refr and agnd. the output full-scale current is equal to 32 x v refo /r set . 33, 39 av dd anal og p ow er inp ut. s ee the p ow er s up p l i es, byp assi ng , d ecoup l i ng , and layout secti on for m or e d etai l s. 34 outnb channel b negative analog current output 35 outpb channel b positive analog current output 36, 40 agnd analog ground 37 outna channel a negative analog current output 38 outpa channel a positive analog current output ep exposed paddle. connect ep to the common point of all ground planes. 10-bit daca channel a gain control da0 da1 da2/g0 da3/g1 da4/g2 da5/g3 da6/ren da7/ide da8/dacen da9/pd daca input register db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 dacb input register control word cw g0 g1 g2 operating mode controller dacen pd g3 input data interleaver 10-bit dacb clock distribution 1.24v reference and control amplifier clock power management dce clkxp clkxn clk digital power management analog power management MAX5853 dv dd dgnd cv dd cgnd ide ren refr refo r set agnd outnb outpb outna outpa agnd av dd figure 2. simplified diagram
MAX5853 dual, 10-bit, 80msps, current-output dac 12 ______________________________________________________________________________________ device power-up and states of operation at power-up, the MAX5853 s default configuration is inter- nal reference, noninterleaved input mode with a gain of 0db and a fully operational converter. in shutdown, the MAX5853 consumes only 1a of supply current, and in standby the current consumption is 3.1ma. wake-up time from standby mode to normal operation is 3s. clock modes the MAX5853 allows both single-ended cmos and dif- ferential clock mode operation, and supports update rates of up to 80msps. these modes are selected through an active-low control line called dce . in single- ended clock mode ( dce = 1), the clk pin functions as an input, which accepts a user-provided single-ended clock signal. data is written to the converter on the rising edge of the clock. the dac outputs (previous data) are updated simultaneously on the same edge. if the dce pin is pulled low, the MAX5853 operates in differential clock mode. in this mode, the clock signal has to be applied to the differential clock input pins clkxp/clkxn. the differential input accepts an input range of 0.5v p-p and a common-mode range of 1v to (cv dd - 0.5v), making the part ideal for low-input ampli- tude clock drives. clkxp/clkxn also help to minimize the jitter, and allow the user to connect a crystal oscilla- tor directly to the MAX5853. the clk pin now becomes an output, and provides a sin- gle-ended replica of the differential clock signal, which may be used to synchronize the input data. data is writ- ten to the device on the rising edge of the clk signal. control word function pd power-down. the part enters power-down mode if pd = 1. dacen dac enable. when dacen = 0 and pd = 0, the part enters standby mode. ide interleaved data mode. ide = 1 enables the interleaved data mode. in this mode, digital data for both channels is applied through channel a in a multiplexed fashion. channel b data is written on the falling edge of the clock signal and channel a data is written on the rising edge of the clock signal. ren reference enable bit. ren = 0 activates the internal reference. ren = 1 disables the internal reference and requires the user to apply an external reference between 0.1v to 1.32v. g3 bit 3 (msb) of gain adjust word g2 bit 2 of gain adjust word g1 bit 1 of gain adjust word g0 bit 0 (lsb) of gain adjust word table 1. control word format and function gain adjustment on channel a (db) g3 g2 g1 g0 +0.4 0000 0 1000 -0.35 1111 table 3. gain difference setting x = don t care. msb lsb pd dacen ide ren g3 g2 g1 g0 x x table 2. configuration modes mode pd dacen ide ren normal operation; noninterleaved inputs; internal reference active 0100 normal operation; noninterleaved inputs; internal reference disabled 0101 normal operation; interleaved inputs; internal reference disabled 0111 standby 0 0 x x power-down 1 x x x power-up 0 1 x x
MAX5853 dual, 10-bit, 80msps, current-output dac ______________________________________________________________________________________ 13 i fs c comp * refr i ref refo max4040 1.24v bandgap reference current- source array *compensation capacitor (c comp 100nf). optional external buffer for heavier loads MAX5853 i ref = v ref r set r set agnd agnd ren = 0 figure 3. setting i fs with the internal 1.24v reference and the control amplifier internal reference and control amplifier the MAX5853 provides an integrated 50ppm/ c, 1.24v, low-noise bandgap reference that can be disabled and overridden with an external reference voltage. refo serves either as an external reference input or an inte- grated reference output. if ren = 0, the internal refer- ence is selected and refo provides a 1.24v (50a) output. buffer refo with an external amplifier, when driving a heavy load. the MAX5853 also employs a control amplifier designed to simultaneously regulate the full-scale out- put current (i fs ) for both outputs of the devices. calculate the output current as: i fs = 32 ? i ref where i ref is the reference output current (i ref = v refo / r set ) and i fs is the full-scale output current. r set is the reference resistor that determines the amplifier out- put current of the MAX5853 (figure 3). this current is mir- rored into the current-source array where i fs is equally distributed between matched current segments and summed to valid output current readings for the dacs. external reference to disable the internal reference of the MAX5853, set ren = 1. apply a temperature-stable, external reference to drive the refo pin and set the full-scale output (figure 4). for improved accuracy and drift performance, choose a fixed output voltage reference such as the 1.2v, 25ppm/ c max6520 bandgap reference. detailed timing the MAX5853 accepts an input data and dac con- version rate of up to 80msps. the input latches on the rising edge of the clock, whereas the output latches on the following rising edge. figure 5 depicts the write cycle of the two dacs in non- interleaved mode. the MAX5853 can also operate in an interleaved data mode. programming the ide bit with a high level activates this mode (tables 1 and 2). in interleaved mode, data for both dac channels is written through input port a. channel b data is written on the falling edge of the clock signal and then channel a data is written on the following rising edge of the clock signal. both dac outputs (chan- nel a and b) are updated simultaneously on the next fol- lowing rising edge of the clock. the interleaved data mode is attractive for applications where lower data rates are acceptable and interfacing on a single 10-bit bus is desired (figure 6). av dd external 1.2v reference max6520 agnd 0.1 f 10 f av dd agnd i fs refr i ref refo 1.24v bandgap reference current- source array MAX5853 r set agnd ren = 1 figure 4. MAX5853 with external reference
MAX5853 dual, 10-bit, 80msps, current-output dac 14 ______________________________________________________________________________________ clkxn clkxp clk output cw da0?a9 outpa outna outpb outnb t cxl t cxh t cdh t cdl t dcs t dch t dcs t dch t cs t cw t cwl daca dacb + 1 daca + 1 control word dacb + 2 daca + 2 daca - 1 dacb - 1 daca dacb daca + 1 dacb + 1 figure 6. timing diagram for interleaved data mode (ide = 1) clkxn clkxp clk output cw da0 da9 outpa outna db0 db9 outpb outnb daca - 1 dacb - 1 daca dacb daca + 1 dacb + 1 daca + 2 dacb + 2 control word xxxx daca + 3 dacb + 3 daca - 1 dacb - 1 daca dacb daca + 1 dacb + 1 daca + 2 dacb + 2 xxxx (control word data) xxxx daca + 3 dacb + 3 t cxh t cxl t cdh t cdl t dcs t dch t dcs t dch t cwl t cs t cw figure 5. timing diagram for noninterleaved data mode (ide = 0)
MAX5853 dual, 10-bit, 80msps, current-output dac ______________________________________________________________________________________ 15 da0 da9 10 MAX5853 1/2 50 ? 100 ? 50 ? outpa outna v outa , single ended db0 db9 10 MAX5853 1/2 50 ? 100 ? 50 ? outpb outnb v outb , single ended cv dd dv dd av dd cgnd dgnd agnd figure 7. application with output transformer performing differential-to-single-ended conversion da0 da9 10 MAX5853 1/2 1/2 50 ? 50 ? cv dd dv dd av dd cgnd dgnd agnd outpa outna db0 db9 10 MAX5853 50 ? 50 ? outpb outnb figure 8. application with dc-coupled differential outputs applications information differential-to-single-ended conversion the MAX5853 exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order qam modulation with ofdm. figure 7 shows a typical application circuit with output transformers performing the required differential-to- single-ended signal conversion. in this configuration, the MAX5853 operates in differential mode, which reduces even-order harmonics, and increases the available output power. differential dc-coupled configuration figure 8 shows the MAX5853 output operating in differ- ential, dc-coupled mode. this configuration can be used in communication systems employing analog quadrature upconverters and requiring a baseband sampling, dual-channel, high-speed dac for i/q syn- thesis. in these applications, information bandwidth can extend from 10mhz down to several hundred kilohertz. dc-coupling is desirable to eliminate long discharge time constants that are problematic with large, expen- sive coupling capacitors. analog quadrature upcon- verters have a dc common-mode input requirement of typically 0.7v to 1.0v. the MAX5853 differential i/q out- puts can maintain the desired full-scale level at the required 0.7v to 1.0v dc common-mode level when powered from a single 2.85v (5%) supply. the MAX5853 meets this low-power requirement with mini- mal reduction in dynamic range while eliminating the need for level-shifting resistor networks. power supplies, bypassing, decoupling, and layout grounding and power-supply decoupling strongly influ- ence the MAX5853 performance. unwanted digital crosstalk can couple through the input, reference,
MAX5853 dual, 10-bit, 80msps, current-output dac 16 ______________________________________________________________________________________ * vias connect the land pattern to internal or external copper planes. power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio or spurious-free dynamic range. in addition, electro- magnetic interference (emi) can either couple into or be generated by the MAX5853. observe the grounding and power-supply decoupling guidelines for high- speed, high-frequency applications. follow the power supply and filter configuration to realize optimum dynamic performance. use of a multilayer printed circuit (pc) board with sepa- rate ground and power-supply planes is recommend- ed. run high-speed signals on lines directly above the ground plane. the MAX5853 has separate analog and digital ground buses (agnd, cgnd, and dgnd, respectively). provide separate analog, digital, and clock ground sections on the pc board with only one point connecting the three planes. the ground connec- tion points should be located underneath the device and connected to the exposed paddle. run digital sig- nals above the digital ground plane and analog/clock signals above the analog/clock ground plane. digital signals should be kept away from sensitive analog, clock, and reference inputs. keep digital signal paths short and metal trace lengths matched to avoid propa- gation delay and data skew mismatch. the MAX5853 includes three separate power-supply inputs: analog (av dd ), digital (dv dd ), and clock (cv dd ). use a single linear regulator power source to branch out to three separate power-supply lines (av dd , dv dd , cv dd ) and returns (agnd, dgnd, cgnd). filter each power-supply line to the respective return line using lc filters comprising ferrite beads and 10f capacitors. filter each supply input locally with 0.1f ceramic capacitors to the respective return lines. note: to maintain the dynamic performance of the electrical characteristics , ensure the voltage differ- ence between dv dd , av dd , and cv dd does not exceed 150mv. thermal characteristics and packaging thermal resistance 40-lead thin qfn-ep: ja = 38 c/w the MAX5853 is packaged in a 40-pin thin qfn-ep package, providing greater design flexibility, increased thermal efficiency, and optimized ac performance of the dac. the ep enables the implementation of grounding techniques, which are necessary to ensure highest performance operation. in this package, the data converter die is attached to an ep leadframe with the back of this frame exposed at the package bottom surface, facing the pc board side of the package. this allows a solid attachment of the pack- age to the pc board with standard infrared (ir) flow sol- dering techniques. a specially created land pattern on the pc board, matching the size of the ep (4.1mm ? 4.1mm), ensures the proper attachment and grounding of the dac. designing vias* into the land area and implementing large ground planes in the pc board design allows for highest performance operation of the dac. use an array of 3 ? 3 vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 40- pin thin qfn-ep package (package code: t4066-1). dynamic performance parameter definitions total harmonic distortion (thd) thd is the ratio of the rms sum of all essential harmon- ics (within a nyquist window) of the input signal to the fundamental itself. this can be expressed as: where v 1 is the fundamental amplitude, and v 2 through v n are the amplitudes of the 2nd through nth order har- monics. the MAX5853 uses the first seven harmonics for this calculation. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal component) to the rms value of their next-largest spectral component. sfdr is usu- ally measured in dbc with respect to the carrier fre- quency amplitude or in dbfs with respect to the dac s full-scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. multitone power ratio (mtpr) a series of equally spaced tones are applied to the dac with one tone removed from the center of the range. mtpr is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequen- cies), which appears as the largest spur at the frequency of the missing tone in the sequence. this test can be per- formed with any number of input tones; however, four and eight tones are among the most common test conditions for cdma- and gsm/edge-type applications. thd vvv v v n = ++ + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? log ... ... 20 2 2 3 2 4 22 1
MAX5853 dual, 10-bit, 80msps, current-output dac ______________________________________________________________________________________ 17 intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc of either out- put tone to the worst 3rd-order (or higher) imd products. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. for a dac, the deviations are measured at every individual step. differential nonlinearity (dnl) differential nonlinearity (dnl) is the difference between an actual step height and the ideal value of 1 lsb. a dnl error specification no more negative than -1 lsb guarantees monotonic transfer function. offset error offset error is the current flowing from positive dac output when the digital input code is set to zero. offset error is expressed in lsbs. gain error a gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. the ideal current is defined by reference voltage at v refo / i ref x 32. settling time the settling time is the amount of time required from the start of a transition until the dac output settles to its new output value to within the converter s specified accuracy. glitch impulse a glitch is generated when a dac switches between two codes. the largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011 111 to 100 000. this occurs due to timing variations between the bits. the glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. the glitch impulse is usu- ally specified in pv-s. chip information transistor count: 9,035 process: cmos table 4. part selection table part speed (msps) resolution max5851 80 8-bit, dual max5852 165 8-bit, dual MAX5853 80 10-bit, dual max5854 165 10-bit, dual
MAX5853 dual, 10-bit, 80msps, current-output dac maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l d 1 2 21-0141 package outline 36,40l thin qfn, 6x6x0.8 mm 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. d 2 2 21-0141 package outline 36, 40l thin qfn, 6x6x0.8 mm

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